? semiconductor components industries, llc, 2006 march, 2006 ? rev. 5 1 publication order number: MC100LVE210/d MC100LVE210 3.3vecl dual 1:4, 1:5 differential fanout buffer description the MC100LVE210 is a low voltage, low skew dual differential ecl fanout buffer designed with clock distribution in mind. the device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. the device features fully differentia l clock paths to minimize both device and system skew. the dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part ? to ? part skew down to an output ? to ? output skew. this capability reduces the skew by a factor of 4 as compared to using two lve111?s to accomplish the same task. to ensure that the tight skew specification is met it is necessary that both sides of the differential output are iden tically terminated, even if only one side is being used. in most applicati ons all nine differential pairs will be used and therefore terminat ed. in the case where fe wer than nine pairs are used it is necessary to terminate at least the output pairs adjacent to the output pair being used in order to maintain minimum skew. failure to follow this guideline will result in small degradations of propagation delay (on the order of 10 ? 20 ps) of the outputs being used, while not catastrophic to most designs this will result in an increase in sk ew. note that the package corners isolate outputs from one another such th at the guideline expressed above holds only for outputs on the same side of the package. the MC100LVE210, as with most ecl devices, can be operated from a positive v cc supply in pecl mode. this allows the lve210 to be used for high performance clock distributio n in +3.3 v systems. designers can take advantage of the lve210?s performance to distribute low skew clocks across the backplane or the board. in a pecl environment series or thevenin line terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage of v cc ? 2.0 v will need to be provided. for more information on using pecl, designers should refer to application note an1406/d. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourci ng or sinking to 0.5 ma. when not used, v bb should be left open. features ? 200 ps part ? to ? part skew ? 50 ps typical output ? to ? output skew ? the 100 series contains temperature compensation ? pecl mode operating range: v cc = 3.0 v to 3.8 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = ? 3.0 v to ? 3.8 v ? internal input pulldown resistors ? q output will default low with inputs open or at v ee ? pb ? free packages are available* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. plcc ? 28 fn suffix case 776 marking diagram* *for additional marking information, refer to application note and8002/d. a = assembly location wl = wafer lot yy = year ww = work week g= pb ? free package MC100LVE210g awlyyww 128 http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information
MC100LVE210 http://onsemi.com 2 1 56 7891011 25 24 23 22 21 20 19 26 27 28 2 3 4 18 17 16 15 14 13 12 v ee v bb clka v cc clka clkb clkb qa3 qa3 qb0 v cco qb0 qb1 qb1 pinout: 28 ? lead plcc (top view) qa0 qa0 qa1 v cco qa1 qa2 qa2 qb4 qb3 qb2 qb4 v cco qb3 qb2 figure 1. pinout assignment warning: all v cc , v cco , and v ee pins must be externally connected to power supply to guarantee proper operation. table 1. pin description pin function clka, clka figure 2. logic diagram table 2. attributes characteristic value internal input pulldown resistor 50 k internal input pullup resistor n/a esd protection human body model machine model > 2 kv > 200 v moisture sensitivity, indefinite time out of drypack (note 1) pb pkg pb ? free pkg plcc ? 28 level 1 level 3 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 179 meets or exceeds jedec standard eia/jesd78 ic latchup test 1. for additional moisture sensitivity information, refer to application note and8003/d.
MC100LVE210 http://onsemi.com 3 table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc pecl mode power supply v ee = 0 v 8 to 0 v v ee necl mode power supply v cc = 0 v ? 8 to 0 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 to 0 ? 6 to 0 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm plcc ? 28 plcc ? 28 63.5 43.5 c/w c/w jc thermal resistance (junction ? to ? case) standard board plcc ? 28 22 to 26 5% c/w t sol wave solder <2 to 3 sec @ 248 c 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
MC100LVE210 http://onsemi.com 4 table 4. lvpecl dc characteristics v cc = 3.3 v; v ee = 0.0 v (note 2) ? 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 55 65 ma v oh output high voltage (note 3) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mv v ol output low voltage (note 3) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mv v ih input high voltage (single ? ended) 2135 2420 2135 2420 2135 2420 mv v il input low voltage (single ? ended) 1490 1825 1490 1825 1490 1825 mv v bb output voltage reference 1.92 2.04 1.92 2.04 1.92 2.04 v v ihcmr input high voltage common mode range (differential) (note 7) 1.8 2.9 1.8 2.9 1.8 2.9 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. input and output parameters vary 1:1 with v cc . v ee can vary 0.3 v. 3. outputs are terminated through a 50 resistor to v cc ? 2.0 v. 4. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . v ihcmr is defined as the range within which the v ih level may vary, with the device still meeting the propagation delay specification. the v il level must be such that the peak to peak voltage is less than 1.0 v and greater than or equal to v pp (min). table 5. lvnecl dc characteristics v cc = 0.0 v; v ee = ? 3.3 v (note 5) ? 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 55 65 ma v oh output high voltage (note 6) ? 1085 ? 1005 ? 880 ? 1025 ? 955 ? 880 ? 1025 ? 955 ? 880 mv v ol output low voltage (note 6) ? 1830 ? 1695 ? 1555 ? 1810 ? 1705 ? 1620 ? 1810 ? 1705 ? 1620 mv v ih input high voltage (single ? ended) ? 1165 ? 880 ? 1165 ? 880 ? 1165 ? 880 mv v il input low voltage (single ? ended) ? 1810 ? 1475 ? 1810 ? 1475 ? 1810 ? 1475 mv v bb output voltage reference ? 1.38 ? 1.26 ? 1.38 ? 1.26 ? 1.38 ? 1.26 v v ihcmr input high voltage common mode range (differential) (note 7) ? 1.5 ? 0.4 ? 1.5 ? 0.4 ? 1.5 ? 0.4 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . v ee can vary 0.3 v. 6. outputs are terminated through a 50 resistor to v cc ? 2.0 v. 7. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . v ihcmr is defined as the range within which the v ih level may vary, with the device still meeting the propagation delay specification. the v il level must be such that the peak to peak voltage is less than 1.0 v and greater than or equal to v pp (min).
MC100LVE210 http://onsemi.com 5 table 6. ac characteristics v cc = 3.3 v; v ee = 0.0 v or v cc = 0.0 v; v ee = ? 3.3 v (note 8) ? 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency 700 700 700 ghz t plh t phl propagation delay to output in (differential) (note 9) in (single ? ended) (note 10) 475 400 675 700 500 450 700 750 500 450 700 750 ps t skew within ? device skew (note 11) qa to qb qa to qa, qb to qb part ? to ? part skew (diff) 50 50 75 75 200 50 30 75 50 200 50 30 75 50 200 ps t jitter cycle ? to ? cycle jitter < 1 < 1 < 1 ps v pp input swing (note 12) 500 1000 500 1000 500 1000 mv t r /t f output rise/fall time (20% ? 80%) 200 600 200 600 200 600 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. v ee can vary 0.3 v. 9. the differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 10. the single ? ended propagation delay is defined as the delay from the 50% point of the input signal to the crossing point of the dif ferential output signals. 11. the within ? device skew is defined as the worst case difference between any two similar delay paths within a single device. 12. v pp (min) is defined as the minimum input dif ferential voltage which will cause no increase in the propagation delay. the v pp (min) is ac limited for the lve210 as a differential input as low as 50 mv will still produce full ecl levels at the output.
MC100LVE210 http://onsemi.com 6 figure 3. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v ordering information device package shipping ? MC100LVE210fn plcc ? 28 37 units / rail MC100LVE210fng plcc ? 28 (pb ? free) 37 units / rail MC100LVE210fnr2 plcc ? 28 500 tape & reel MC100LVE210fnr2g plcc ? 28 (pb ? free) 500 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1642/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
MC100LVE210 http://onsemi.com 7 package dimensions plcc ? 28 fn suffix plastic package case 776 ? 02 issue e ? n ? ? m ? ? l ? v w d d y brk 28 1 view s s l?m s 0.010 (0.250) n s t s l?m m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s l?m m 0.007 (0.180) n s t ? t ? b s l?m s 0.010 (0.250) n s t s l?m m 0.007 (0.180) n s t u s l?m m 0.007 (0.180) n s t z g1 x view d ? d s l?m m 0.007 (0.180) n s t k1 view s h k f s l?m m 0.007 (0.180) n s t notes: 1. datums ?l?, ?m?, and ?n? determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum ?t?, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 ??? 0.51 ??? k 0.025 ??? 0.64 ??? r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y ??? 0.020 ??? 0.50 z 2 10 2 10 g1 0.410 0.430 10.42 10.92 k1 0.040 ??? 1.02 ???
MC100LVE210 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 MC100LVE210/d eclinps is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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